1. Field of the Invention
The present invention relates to computer systems, and particularly to processors, such as processors for digital signal processing (DSP's), and to a method for handling the transfer of guarded instructions in such computer systems.
2. Discussion of Related Art
A computer system affected by the present invention generally may include several processing units operating in parallel. Typical processing units may include an arithmetic and logic unit, an addressing unit and a branch-handling unit. In addition to these processing units, the computer system generally includes a control unit or central unit which carries on a dialogue with the program memory and issues individual instructions, also widely called micro-instructions, to the various processing units.
Among the instructions issued to the processing units, are included instructions called “guarded” instructions allowing higher-performance writing of the program code. A guarded instruction is an instruction assigned an indication called a guard indicator so that the execution or otherwise of the instruction is dependent upon the value of the guard indicator. The use of guarded instructions in a processor or computer system is already known to the person skilled in the art, for example from the European Patent Application No. 1 050 803 which is incorporated herein by reference. The principle of guarded instructions is reiterated briefly here; the person skilled in the art can refer for further details, if necessary, to the above-mentioned European Patent Application.
In practice, the guard indicator is typically a guard bit capable of taking the value 0 or 1. The guarded instruction will be executed or not executed depending on the value of the guard bit, that is to say on the guard indication. All the binary values of the guard indications, possibly numbering sixteen for example, are contained in a register called “guard-indication register”. This centralized register is incorporated within a processing unit, for example the arithmetic and logic unit, and, at every instant, contains the current values of the guard indications or bits. The values of these guard indications can be modified by specific instructions called “modifying instructions.”
In order to read the value of a guard indication associated with a guarded instruction, the processing unit which receives this guarded instruction, and which does not have direct access to the guard-indication register (for example the branching unit), requires a transfer of the value of the guard indication from the processing unit which is holding the guard-indication register. In other words, the issuing of a guarded instruction to a processing unit which does not hold the guard-indications register causes the issuing to the processing unit which is the holder of the guard-indications register of an instruction called a “transmission” instruction, which is intended to make the processing unit which receives the guarded instruction transmit the value of the guard indication associated with this guarded instruction.
The guarded instruction is kept in the header stage (output stage) of the FIFO first in/first out-type instruction memory associated with this processing unit, until the latter receives, from the processing unit which is holding the guard-indications register, said guard-indications value associated with this guarded instruction. It is only when the processing unit which holds the guard-indications register has executed the transmission instruction that the corresponding value of the guard indication will be transmitted to the requesting processing unit, so that it can execute or not execute its guarded instruction.
In a computer system which requires the transfer of guard values between parallel execution units, it is important that the transfer of guard values is accomplished as promptly and efficiently as possible. This, however, should be done without transferring incorrect guard values and, preferably, without stalling the operation of the pipelined execution units.
If, for one reason or another, the transmission instruction is blocked in the instruction memory of the processing unit which holds the guard-indications register, the requesting unit will consequently also be blocked until it receives the value of the corresponding guard indication. Problems sometimes arise when a plurality of instructions are executed simultaneously in a plurality of parallel execution units. This may arise in computer systems operating in superscalar or very long instruction word (VLIW) instruction modes so that the execution of some instructions may affect the guard values to be associated with other instructions in parallel execution units. Problems may also arise from pipelined execution of instructions so that the execution of some later instructions commences prior to the completion of execution of earlier instructions in the pipeline.
The invention envisages affording a solution to these problems.